1. Field of the Invention
One embodiment of the present invention relates to a semiconductor device. For example, one embodiment of the present invention relates to a semiconductor device including a logic circuit which can perform a scan test.
2. Description of the Related Art
One of methods for verifying whether a manufactured semiconductor device operates correctly is a scan test. In the scan test, a plurality of sequential circuits included in a semiconductor device are connected in series in operation verification so that a shift register called a scan chain is formed, and data for verification is directly input from an external input terminal to the scan chain. Then, a logic circuit is operated in accordance with the input data, and data thus output from the logic circuit is directly extracted from the scan chain through an external output terminal. By the above method, the operation of the logic circuit can be verified.
To carry out the scan test, a plurality of sequential circuits are necessarily connected in series only in operation verification, and therefore a multiplexer is provided on the input side of each of the sequential circuits. By providing multiplexers, connection between the sequential circuits can be changed depending on normal operation or operation verification. Patent Document 1 discloses a memory test circuit which includes an input data register formed of a multiplexer and a scan flip-flop.